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ARCS 2011 - Architecture of Computing Systems
» ARCS 2011

Program & Presentations

Conference Program

  • Tuesday, Feb. 22, 2011 - Wednesday, Feb. 23, 2011: Tutorials and Workshops
  • Thursday, Feb. 24, 2011 - Friday, Feb. 25, 2011: Conference

ARCS2011 Preliminary Programme

Conference & Workshops Schedule



DAY 1, February 24, 2011, Morning Sessions

 

Keynote Plenary Session:
"Scalability Challenges for Future Multi/Many-core Architectures"
Per Stenström, Chalmers University of Technology,
Goteborg, Sweden

ABSTRACT
Technology forecasts continue to predict a biennial doubling of the number of processor cores for the next ten years. But the road forward to unleash their computational power to application performance will be increasingly challenging. Some of these challenges concern 1) how architects can provide a more productive interface to the software 2) how the memory system can be architected so that memory bandwidth can scale up exponentially and 3) how to use transistors to make the whole chip infrastructure scalable to a large number of processor cores. This talk will focus on these challenges and highlight a few recent developments that tackle them.

 

Session 1: Customization and application specific accelerators
Session Chair: Pedro Trancoso, University of Cyprus

Title: A Code-based Analytical Approach for Using Separate Device Coprocessors in Computing Systems

Authors: Volker Hampel, Grigori Goronzy, Erik Maehle

Affiliations: Institute of Computer Engineering, University of Luebeck

 

Title: Performance Evaluation of a Polymorphic Register File: a CG Case Study

Authors: Catalin Ciobanu, Xavier Martorell, Georgi Kuzmanov, Alex Ramirez, Georgi Gaydadjiev

Affiliations: Delft University of Technology, Barcelona Supercomputing Center, Universitat Politecnica de Catalunya

 

Title: Experiences with string matching on the Fermi architecture

Authors: Antonino Tumeo, Simone Secchi, Oreste Villa

Affiliations: Pacific Northwest National Laboratory

 

DAY 1, February 24, 2011, Afternoon Sessions

 

Session 2a: Multi/Many-core Architectures
Session Chair: Wolfgang Karl, Karlsruhe Institute of Technology

 

Title: Using Amdahl's Law For Performance Analysis of Many-Core SoC Architectures Based On Functionally Asymmetric Processors

Authors: Hao Shen and Frédéric Pétrot

Affiliations: TIMA Laboratory

 

Title: Application-aware Power Saving for Online Transaction Processing using Dynamic Voltage and Frequency Scaling in a Multicore Environment

Authors: Yuto HAYAMIZU, Kazuo GODA, Miyuki NAKANO and Masaru KITSUREGAWA

Affiliations: University of Tokyo

 

Title: Frameworks for Multi-core Architectures: A Comprehensive Evaluation using 2D/3D Image Registration

Authors: Richard Membarth, Frank Hannig, Juergen Teich, Mario Koerner, and Wieland Eckert

Affiliations: University of Erlangen-Nuremberg

 

Session 2b: Adaptive System Architectures
Session Chair: Christian Mueller-Schloer, Leibniz Universitaet Hannover

 

Title: Emulating transactional memory on FPGA multiprocessors

Authors: Matteo Pusceddu, Simone Ceccolini, Antonino Tumeo, Gianluca Palermo, Donatella Sciuto

Affiliations: Politecnico di Milano, Pacific Northwest National Laboratory

 

Title: Architecture of an Adaptive Test System Built on FPGAs

Authors: Joerg Sachsse, Heinz-Dietrich Wuttke, Steffen Ostendorff, Jorge Hern´n Meza Escobar

Affiliations: Ilmenau University of Technology

 

Title: An Extensible Framework for Context-Aware Smart Environments

Authors: A. Abdulahad Sabagh and A. Al-Yasiri

Affiliations: University of Salford, UK

 

Session 3a: Processor Architectures
Session Chair: Vittorio Zaccaria, Politecnico di Milano

 

Title: Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3

Authors: Jaroslav Sykora, Leos Kafka, Martin Danek, Lukas Kohout

Affiliations: UTIA AV CR, v.v.i.

 

Title: A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware

Authors: Stefan Metzlaff, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer

Affiliations: University of Augsburg, Germany and TU Dortmund, Germany

 

Title: Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy

Authors: Marius Grannaes, Magnus Jahre and Lasse Natvig

Affiliations: Norwegian University of Science and Technology

 

Session 3b: Memory Architectures Optimisation
Session Chair: Theo Ungerer, University of Augsburg

 

Title: Compiler-assisted Selection of a Software Transactional Memory System

Authors: Martin Schindewolf, Alexander Esselson, Wolfgang Karl

Affiliations: Karlsruhe Institute of Technology (KIT)

 

Title: An Instruction to Accelerate Software Caches

Authors: Arnaldo Azevedo, Ben Juurlink

Affiliations: TU Delft, TU Berlin

 

Title: Memory-, Bandwidth-, and Power-Aware Multi-core for a Graph Database Workload

Authors: Pedro Trancoso, Norbert Martinez, Josep-Lluis Larriba-Pey

Affiliations: University of Cyprus, Universitat Politecnica de Catalunya

 

DAY 2, February 25, 2011, Morning Sessions

 

Keynote Plenary Session:
"Microprocessor architecture and Process Variability, challenges and opportunities"
Giuseppe Desoli, Advanced Systems Technology, STMicroelectronics,
Italy

ABSTRACT
With ever shrinking device geometries in deep sub-nanometer technologies, the effects of on­chip variations more deeply affect digital circuit behavior. Variations arise from fluctuations associated to the manufacturing process such as in channel length, oxide thickness, threshold voltage, doping concentration, etc. It is now generally understood in the VLSI design and EDA community and industry that those are serious problems affecting yield, operating conditions (e.g., supply voltage or temperature), timing and power, so much that a variation tolerant design is key for next generation devices. However effective design and process improvements can be at reducing the adverse effects of variability, time is quickly approaching for microprocessors and SoC architects to be summoned to this battle. This talk will provide a quick overview of how tackling the problem at a higher level can help; starting from an analysis of the relevant phenomena and their impact once projected at the architecture level; and then illustrating some of the current state of the art proposed solution both in academia and industry.

 

Session 4: Organic and Autonomic Computing
Session Chair: Juergen Brehm, Leibniz Universitaet Hannover

 

Title: A Light-Weight Approach for Online State Classification of Self-Organizing Parallel Systems

Authors: David Kramer, Rainer Buchty, Wolfgang Karl

Affiliations: Karlsruhe Institute of Technology (KIT)

 

Title: Towards Organic Active Vision Systems for Visual Surveillance

Authors: Michael Wittke, Carsten Grenz, Joerg Haehner

Affiliations: Leibniz Universitaet Hannover, Institute of Systems Engineering, System and Computer Architecture, 30167 Hannover, Germany

 

Title: Emergent Behaviour in Collaborative Indoor Location: an Example of Self-organization in Ubiquitous Sensing Systems

Authors: Kamil Kloch, Gerald Pirkl, Paul Lukowicz, Carl Fischer

Affiliations: Embedded Systems Lab, University of Passau and Computing Department, Lancaster University, UK

 

DAY 2, February 25, 2011, Afternoon Session

 

Session 5: Network-on-Chip Architectures
Session Chair: Gianluca Palermo, Politecnico di Milano

 

Title: An Improvement of Router Throughput for On-Chip Networks using On-the-fly Virtual Channel Allocation

Authors: Son Truong Nguyen and Shigeru Oyanagi

Affiliations: Ritsumeikan University, Japan

 

Title: Energy-optimized On-chip Networks Using Reconfigurable Shortcut Paths

Authors: Nasibeh Teimouri , Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-azad

Affiliations: Sharif University of Technology, Computer engineering department, Iran

 

Title: A Learning-based Approach to the Automated Design of MPSoC Networks

Authors: Oscar Almer, Nigel Topham, Bjorn Franke

Affiliations: The University of Edinburgh

 

Title: Gateway Strategies for Embedding of Automotive CAN-frames into Ethernet-packets and Vice Versa

Authors: Andreas Kern, Dominik Reinhard, Thilo Streichert, Juergen Teich

Affiliations: Daimler AG, University of Erlangen-Nuremberg

 

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