1st ERDIAP Workshop
Exploiting Regularity in the Design of IPs, Architectures and Platforms
Como, Italy - February 23, 2011


With the introduction of advanced process nodes, new and significant layout restrictions lead to a more regular layout style. The ERDIAP workshop targets the optimization of manufacturability and the reduction of systematic variations in nanometer technologies through exploitation of regularity at the architectural, structural, and geometrical levels.

Topics of interest include, but are not limited to:

  • Architectures tolerant to process variation
  • Regular architectures
  • Applications of regular architectures
  • Physical design of regular architectures
  • Automatic regularity extraction at structural and functional level
  • Regularity-aware logic synthesis
  • Lithography-friendly circuit layout
  • Design of memories under process variation
  • Characterization of the layout effects imposed by regularity

ERDIAP is connected with the SYNAPTIC FP7 project (http://www.synaptic-project.eu) and it will be held on February 23rd, 2011 in conjunction with ARCS (Architecture of Computing Systems) 2011, Como, Italy (http://conferences.dei.polimi.it/arcs2011).

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